MK2069-04集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書(shū)PDF中文資料

Features

? Input clock frequency <1 kHz to 170 MHz

? Output clock frequency of 500 kHz to 160 MHz

? Clock translation examples:

T1 (1.544 MHz) to/from E1 (2.048 MHz)

T3 (44.736 MHz) to/from E3 (34.368 MHz)

OC-3 (155.52 MHz) to/from T1 (1.544 MHz)

CCIR-601 (27 MHz) to/from SMPTE 274M (74.125

MHz)

? Jitter attenuation of input clock provided by VCXO circuit.

Jitter transfer characteristics user configured through

external loop filter component selection.

? Low jitter and phase noise generation.

? PLL lock status output

? PLL Clear function allows seamless synchronizing to an

altered input clock phase

? 2nd PLL provides frequency translation of VCXO PLL

output (VCLK) to a higher or alternate output frequency

(TCLK).

? Device will free-run in the absence of an input clock

based on VCXO frequency.

? 56-pin TSSOP package

? Single 3.3 V power supply

? 5 V tolerant clock input

? Pb (lead) free package