MM54HCT193J中文資料美國國家半導體數據手冊PDF規(guī)格書

General Description

These high speed synchronous counters utilize advanced

silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of CMOS technology,

along with the speeds of low power Schottky TTL. The

MM54HCT193/MM74HCT193 is a binary counter having

two separate clock inputs, an UP COUNT input and a

DOWN COUNT input. All outputs of the flip-flops are simultaneously triggered on the low-to-high transition of either

clock while the other input is held high. The direction of

counting is determined by which input is clocked.

This device has TTL compatible inputs. It can drive 15 LSTTL loads.

This counter may be preset by entering the desired data on

the DATA A, DATA B, DATA C, and DATA D inputs. When

the LOAD input is taken low, the data is loaded independently of either clock input. This feature allows the counter

to be used as a divide-by-n counter by modifying the count

length with the preset inputs.

In addition, the HCT193 can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4 internal

stages are set to a low level independently of either COUNT

input.

Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions. The

BORROW output produces a negative-going pulse when

the counter underflows and the CARRY outputs a pulse

when the counter overflows. The counter can be cascaded

by connecting the CARRY and BORROW outputs of one

device to the COUNT UP and COUNT DOWN inputs, respectively, of the next device.

All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

Y Low quiescent supply current: 80 mA maximum (74HCT

Series)

Y Low input current: 1 mA maximum

Y TTL compatible inputs