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MNSC140CORE中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
MNSC140CORE |
功能描述 | Quad Core 16-Bit Digital Signal Processor |
文件大小 |
2.76555 Mbytes |
頁(yè)面數(shù)量 |
88 頁(yè) |
生產(chǎn)廠商 | Freescale Semiconductor, Inc |
企業(yè)簡(jiǎn)稱(chēng) |
freescale【飛思卡爾】 |
中文名稱(chēng) | 飛思卡爾半導(dǎo)體官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-12-24 9:16:00 |
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更多MNSC140CORE規(guī)格書(shū)詳情
Quad Digital Signal Processor
? Four StarCore? SC140 DSP extended cores, each with an SC140
DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte
total), 16 way 16 Kbyte instruction cache (ICache), four-entry
write buffer, external cache support, programmable interrupt
controller (PIC), local interrupt controller (LIC), and low-power
Wait and Stop processing modes.
? 475 Kbyte M2 memory for critical data and temporary data
buffering.
? 4 Kbyte boot ROM.
? M2-accessible multi-core MQBus connecting the M2 memory
with all four cores, operating at the core frequency, with data bus
access of up to 128-bit reads and up to 64-bit writes, central
efficient round-robin arbiter for core access to the bus, and atomic
operation control of M2 memory access by the cores and the local
bus.
? Internal PLL configured are reset by configuration signal values.
? 60x-compatible system bus with 64 or 32 bit data and 32-bit
address bus, support for multi-master designs, four-beat burst
transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8
bits controlled by the internal memory controller,.access to
external memory or peripherals, access by an external host to
internal resources, slave support with direct access to internal
resources including M1 and M2 memories, and on-device
arbitration for up to four master devices (Continue ...)
產(chǎn)品屬性
- 型號(hào):
MNSC140CORE
- 制造商:
FREESCALE
- 制造商全稱(chēng):
Freescale Semiconductor, Inc
- 功能描述:
Quad Core 16-Bit Digital Signal Processor
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