MPC185TD中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書

Typical System Architecture

The MPC185 is designed to integrate easily into any system using the 60x bus protocol. It is ideal in any system using a Motorola PowerQUICC II communications processor (as shown in Figure 4-1) or a PowerPC-architectured processor and memory controller. The ability of the MPC185 to be a master on the 60x bus allows the co-processor to offload the data movement bottleneck normally associated with slave devices.

The host processor accesses the MPC185 through its device drivers using system memory for data storage. The MPC185 resides in the memory map of the processor, therefore when an application requires cryptographic functions, it simply creates descriptors for the MPC185 which define the cryptographic function to be performed and the location of the data. The MPC185’s 60x-mastering capability permits the host processor to set up a crypto-channel with a few short register writes, leaving the MPC185 to perform reads and writes on system memory to complete the required task.

Typical Applications

The MPC185 is suited for applications such as the following:

? Edge routers

? Broadband access equipment

? eCommerce servers

? Wireless base stations

? WAP gateways