MPC604E9QEC/D中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

This section summarizes features of the 604e?s implementation of the PowerPC architecture. Major features

of the 604e are as follows:

￥ High-performance, superscalar microprocessor

? As many as four instructions can be issued per clock

? As many as seven instructions can start executing per clock (including three integer

instructions)

? Single-clock-cycle execution for most instructions

￥ Seven independent execution units and two register Tles

? BPU featuring dynamic branch prediction

D Two-entry reservation station

D Out-of-order execution through two branches

D Shares dispatch bus with CRU

D 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can

be disabled and invalidated.

D 512-entry branch history table (BHT) with two bits per entry for four levels of prediction?

not-taken, strongly not-taken, taken, strongly taken

? Condition register logical unit

D Two-entry reservation station

D Shares dispatch bus with BPU

? Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)

D Instructions that execute in the SCIU take one cycle to execute; most instructions that

execute in the MCIU take multiple cycles to execute.

D Each SCIU has a two-entry reservation station to minimize stalls

D The MCIU has a single-entry reservation station and provides early exit (three cycles) for

16- x 32-bit and over?ow operations.

D Thirty-two GPRs for integer operands

? Three-stage ?oating-point unit (FPU)

D Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

D Supports non-IEEE mode for time-critical operations

D Fully pipelined, single-pass double-precision design

D Hardware support for denormalized numbers

D Two-entry reservation station to minimize stalls

D Thirty-two 64-bit FPRs for single- or double-precision operands

? Load/store unit (LSU)

D Two-entry reservation station to minimize stalls

D Single-cycle, pipelined cache access

D Dedicated adder performs effective address (EA) calculations

D Performs alignment and precision conversion for ?oating-point data

D Performs alignment and sign extension for integer data

D Four-entry Tnish load queue (FLQ) provides load miss buffering

D Six-entry store queue

D Supports both big- and little-endian modes

￥ Rename buffers

? Twelve GPR rename buffers

? Eight FPR rename buffers

? Eight condition register (CR) rename buffers

￥ Completion unit

? The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has Tnished execution.

? Guarantees sequential programming model (precise exception model)

? Monitors all dispatched instructions and retires them in order

? Tracks unresolved branches and ?ushes executed, dispatched, and fetched instructions if branch

is mispredicted

? Retires as many as four instructions per clock

￥ Separate on-chip instruction and data caches (Harvard architecture)

? 32-Kbyte, four-way set-associative instruction and data caches

? LRU replacement algorithm

? 32-byte (eight-word) cache block size

? Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical

address space as real address space.)

? Cache write-back or write-through operation programmable on a per page or per block basis

? Instruction cache can provide four instructions per clock; data cache can provide two words per

clock

? Caches can be disabled in software

? Caches can be locked

? Parity checking performed on both caches

? Data cache coherency (MESI) maintained in hardware

? Secondary data cache support provided

? Instruction cache coherency maintained in hardware

? Data cache line-Tll buffer forwarding. In the 604 only the critical double word of the cache

block was made available to the requesting unit at the time it was burst into the line-Tll buffer.

Subsequent data was unavailable until the cache block was Tlled. On the 604e, subsequent data

is also made available as it arrives in the line-Tll buffer.

￥ Separate memory management units (MMUs) for instructions and data

? Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

? Both TLBs are 128-entry and two-way set associative

? TLBs are hardware reloadable (that is, the page table search is performed in hardware)

? Separate IBATs and DBATs (four each) also deTned as SPRs

? Separate instruction and data translation lookaside buffers (TLBs)

? LRU replacement algorithm

? 52-bit virtual address; 32-bit physical address

￥ Bus interface features include the following:

? Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, 5:1,

11:2, 6:1, 13:2, and 7:1)

? A 64-bit split-transaction external data bus with burst transfers

? Support for address pipelining and limited out-of-order bus transactions

? Four burst write queues?three for cache copyback operations and one for snoop push

operations

? Two single-beat write queues

? Additional signals and signal redeTnition for direct-store operations

? Provides a data streaming mode that allows consecutive burst read data transfers to occur

without intervening dead cycles. This mode also disables data retry operations.

? No-DRTRY mode eliminates the DRTRY signal from the qualiTed bus grant and allows read

operations. This improves performance on read operations for systems that do not use the

DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock

cycle sooner than if normal mode is used.

￥ Multiprocessing support features include the following:

? Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are

provided in the instruction cache to indicate only whether a cache block is valid or invalid.

? Separate port into data cache tags for bus snooping

? Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

￥ Power management

? NAP mode supports full shut down and snooping

? Operating voltage of 1.9 ± 100 mV

￥ Performance monitor can be used to help in debugging system designs and improving software

efTciency, especially in multiprocessor systems.

￥ In-system testability and debugging features through JTAG boundary-scan capability