MPR603TSU-03中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

PowerPC 603 Microprocessor Features

This section describes details of the 603’s implementation of the PowerPC architecture. Major features of

the 603 are as follows:

? High-performance, superscalar microprocessor

— As many as three instructions issued and retired per clock

— As many as five instructions in execution per clock

— Single-cycle execution for most instructions

— Pipelined FPU for all single-precision and most double-precision operations

? Five independent execution units and two register files

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for both single- and double-precision operations

— LSU for data transfer between data cache and GPRs and FPRs

— SRU that executes condition register (CR) and special-purpose register (SPR) instructions

— Thirty-two GPRs for integer operands

— Thirty-two FPRs for single- or double-precision operands

? High instruction and data throughput

— Zero-cycle branch capability (branch folding)

— Programmable static branch prediction on unresolved conditional branches

— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

— A six-entry instruction queue that provides look-ahead capability

— Independent pipelines with feed-forwarding that reduces data dependencies in hardware

— 8-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement

algorithm

— 8-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement

algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

— BPU that performs CR look-ahead operations

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 64-entry, two-way set-associative ITLB

— A 64-entry, two-way set-associative DTLB

— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks

— Software table search operations and updates supported through fast trap mechanism

— 52-bit virtual address; 32-bit physical address

? Facilities for enhanced system performance

— A 32- or 64-bit split-transaction external data bus with burst transfers

— Support for one-level address pipelining and out-of-order bus transactions

— Bus extensions for direct-store interface operations

? Integrated power management

— Low-power 3.3-volt design

— Internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1, and 4/1 ratios

— Three power saving modes: doze, nap, and sleep

— Automatic dynamic power reduction when internal functional units are idle

? In-system testability and debugging features through JTAG boundary-scan capability