MT46V32M4TG-8中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書

GENERAL DESCRIPTION

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quadbank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

FEATURES

? VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

? Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte)

? Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

? Differential clock inputs (CK and CK#)

? Commands entered on each positive CK edge

? DQS edge-aligned with data for READs; centeraligned with data for WRITEs

? DLL to align DQ and DQS transitions with CK

? Four internal banks for concurrent operation

? Data mask (DM) for masking write data (x16 has two – one per byte)

? x16 has programmable IOL/IOH option

? Programmable burst lengths: 2, 4, or 8

? Auto precharge option

? Auto Refresh and Self Refresh Modes

? Longer lead TSOP for improved reliability (OCPL)

? 2.5V I/O (SSTL_2 compatible)