MT48H8M32LFB5-75G中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書

General Description

The Micron? 256Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.

Features

? Fully synchronous; all signals registered on positive edge of system clock

? VDD/VDDQ = 1.70–1.95V

? Internal, pipelined operation; column address can be changed every clock cycle

? Four internal banks for concurrent operation

? Programmable burst lengths: 1, 2, 4, 8, or continuous page1

? Auto precharge, includes concurrent auto precharge

? Auto refresh and self refresh modes

? LVTTL-compatible inputs and outputs

? On-chip temperature sensor to control refresh rate

? Partial-array self refresh (PASR)

? Deep power-down (DPD)

? Selectable output drive (DS)

? 64ms refresh period (8,192 rows)