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MT4C4M4E8DJ中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書

MT4C4M4E8DJ
廠商型號(hào)

MT4C4M4E8DJ

功能描述

4 MEG x 4 EDO DRAM

文件大小

291.14 Kbytes

頁面數(shù)量

23

生產(chǎn)廠商 Micron Technology
企業(yè)簡(jiǎn)稱

Micron鎂光

中文名稱

美國鎂光科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-11-19 16:28:00

MT4C4M4E8DJ規(guī)格書詳情

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are “don’t care”). READ and WRITE cycles are selected with the WE# input.

FEATURES

? Industry-standard x4 pinout, timing, functions and packages

? State-of-the-art, high-performance, low-power CMOS silicon-gate process

? Single power supply (+3.3V ±0.3V or +5V ±10)

? All inputs, outputs and clocks are TTL-compatible

? Refresh modes: RAS#-ONLY, HIDDEN and CAS#-BEFORE-RAS# (CBR)

? Optional Self Refresh (S) for low-power data retention

? 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)

? Extended Data-Out (EDO) PAGE MODE access cycle

? 5V-tolerant inputs and I/Os on 3.3V devices

產(chǎn)品屬性

  • 型號(hào):

    MT4C4M4E8DJ

  • 制造商:

    MICRON

  • 制造商全稱:

    Micron Technology

  • 功能描述:

    4 MEG x 4 EDO DRAM

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
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21+
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35200
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8324
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7000
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絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
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