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MT5C1009CW-15/XT中文資料AUSTIN數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

MT5C1009CW-15/XT
廠商型號(hào)

MT5C1009CW-15/XT

功能描述

128K x 8 SRAM WITH CHIP & OUTPUT ENABLE

文件大小

254.43 Kbytes

頁(yè)面數(shù)量

17 頁(yè)

生產(chǎn)廠商 Austin Semiconductor
企業(yè)簡(jiǎn)稱(chēng)

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更新時(shí)間

2025-1-10 9:10:00

MT5C1009CW-15/XT規(guī)格書(shū)詳情

GENERAL DESCRIPTION

The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle.

For design flexibility in high-speed memory applications, this device offers chip enable (CE) and output enable (OE) features. These enhancements can place the outputs in High-Z for additional flexibility in system design.

The “L” version offers a 2V data retention mode, reducing current consumption to 2mW maximum.

All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. It is particularly well suited for use in high-density, high-speed system applications.

FEATURES

? Access Times: 15, 20, 25, 35, 45, 55 and 70 ns

? Battery Backup: 2V data retention

? Low power standby

? High-performance, low-power CMOS process

? Single +5V (+10) Power Supply

? Easy memory expansion with CE and OE options.

? All inputs and outputs are TTL compatible

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
ASI
2022
NA
80000
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MCT
1995
100
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu)
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ASI
2308+
NA
4862
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23+
原裝正品現(xiàn)貨
10000
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QQ咨詢(xún)
CDIP
135
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24+
NA
990000
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23+
NA/
543
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66800
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