MT5C1009EC-55LSLASHIT中文資料AUSTIN數(shù)據(jù)手冊(cè)PDF規(guī)格書

GENERAL DESCRIPTION

The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle.

For design flexibility in high-speed memory applications, this device offers chip enable (CE) and output enable (OE) features. These enhancements can place the outputs in High-Z for additional flexibility in system design.

The “L” version offers a 2V data retention mode, reducing current consumption to 2mW maximum.

All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. It is particularly well suited for use in high-density, high-speed system applications.

FEATURES

? Access Times: 15, 20, 25, 35, 45, 55 and 70 ns

? Battery Backup: 2V data retention

? Low power standby

? High-performance, low-power CMOS process

? Single +5V (+10%) Power Supply

? Easy memory expansion with CE and OE options.

? All inputs and outputs are TTL compatible