MU9C32K64M-90B568C中文資料MUSIC數據手冊PDF規(guī)格書

GENERAL DESCRIPTION

The MU9C RCP family consists of 4K, 8K, 16K, 24K, and 32K x 64-bit Routing Co-Processors (RCP’s) with a 32-bit wide data interface and a 32-bit ternary compare instruction. The device is designed for use in layer 3 switches, routers, and layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MU9C RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce jitter on the latency of the global system.

DISTINCTIVE CHARACTERISTICS

? 4K, 8K, 16K, 24K, and 32K x 64-bit words

? 32-bit ternary or 64-bit binary compares

? 35 ns deterministic compare and output time

? 32-bit Data I/O port

? 16-bit Match Address Output port

? Address/Control bus directly controls device operations for faster operation or higher throughput

? Seven selectable mask registers

? Synchronous operation

? Cascadable for increased depth

? Extensive set of control states for flexibility

? JTAG interface

? 4K and 8K; 100-pin LQFP package

? 16K, 24K, and 32K; 35mm BGA package

? 3.3 Volt operation

? Lead-free, fully RoHS compatible package available

APPLICATION BENEFITS

? Longest Prefix Match searches of IPv4 addresses

? 28 Million IPv4 packets per second supports up to 18 Gb Ethernet or 7 OC-48 ATM ports at wire speed

? Longest Prefix Match searches of IPv4 addresses

? Exact match on MAC addresses

? Processes DA and SA within 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed

? Mixed mode L3 and L2 single search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed

? Directly addresses external RAM containing associated data of any width

? Hardware control states directly address memory and registers; Instruction and Status registers for optional software control