MX25U25643GZNI00中文資料????????????旺宏數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

GENERAL

? Supports Serial Peripheral Interface -- Mode 0 and

Mode 3

? Single Power Supply Operation

- 1.65 to 2.0 volt for read, erase, and program operations

? 268,435,456 x 1 bit structure or

134,217,728 x 2 bits (two I/O mode) structure or

67,108,864 x 4 bits (four I/O mode) structure

? Protocol Support

- Single I/O, Dual I/O and Quad I/O

? Latch-up protected to 100mA from -1V to Vcc +1V

? Low Vcc write inhibit is from 1.0V to 1.4V

? Fast read for SPI mode

- Support clock frequency up to 133MHz

- Support Fast Read, 2READ, DREAD, 4READ,

QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Configurable dummy cycle number for fast read

operation

? Support Performance Enhance Mode - XIP

(execute-in-place)

? Quad Peripheral Interface (QPI) available

? Equal Sectors with 4K byte each, or Equal Blocks

with 32K byte each or Equal Blocks with 64K byte

each

- Any Block can be erased individually

? Programming:

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance

program performance

? Typical 100,000 erase/program cycles

? 20 years data retention