N74F377AD中文資料飛利浦數(shù)據手冊PDF規(guī)格書
N74F377AD規(guī)格書詳情
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
FEATURES
? High impedance inputs for reduced loading (20μA in Low and High states)
? Ideal for addressable register applications
? Enable for address and data synchronization applications
? Eight edge–triggered D–type flip–flops
? Buffered common clock
? See ’F273A for Master Reset version
? See ’F373 for transparent latch version
? See ’F374 for 3–State version
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
PHILIPS/飛利浦 |
22+ |
DIP-20 |
9600 |
原裝現(xiàn)貨,優(yōu)勢供應,支持實單! |
詢價 | ||
PHI |
97+ |
SOP20 |
1000 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
PHI |
23+ |
SOP20 |
1000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價 | ||
PIL |
2020+ |
DIP2-0 |
80000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
詢價 | ||
NXP/恩智浦 |
23+ |
SOP |
20000 |
原廠授權一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種 |
詢價 | ||
PHILIPS/飛利浦 |
23+ |
SOP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價 | ||
PHI |
SOP20 |
699839 |
集團化配單-有更多數(shù)量-免費送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價 | |||
24+ |
3000 |
公司存貨 |
詢價 | ||||
PHI |
589220 |
16余年資質 絕對原盒原盤 更多數(shù)量 |
詢價 | ||||
NXP |
23+ |
PLCC |
8890 |
價格優(yōu)勢/原裝現(xiàn)貨/客戶至上/歡迎廣大客戶來電查詢 |
詢價 |
