NCA9700中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書

1. General description

The NCA9700 is a dual-channel bidirectional repeater for I2C and SMBus/PMBus applications. It

targets the Fast-mode Plus (Fm+) of the I2C protocol, making the true 1 MHz operation possible

without violating I2C timing specifications. This is achieved by using edge accelerators added at all

NCA9700 ports that speed up the LOW-to-HIGH transitions of I2C input and output signals.

The NCA9700 provides the buffering for both clock (SCL) and data (SDA) I2C signals with the

voltage level translation possibility (up and down) at the same time. The unique feature of the

IC is the same operating voltage range of 1.08 V to 3.6 V that can be applied at both port A

and port B of the device. This offers more flexibility in how the device can be used in the target

application. Multiple NCA9700s can be connected in series or in star, and their ports A and B can

be exchanged. Only when the I2C clock stretching needs to be supported, the NCA9700 port A

must be connected to the I2C Master side and the NCA9700 port B to the I2C Slave side.

The NCA9700 features integrated pull-up resistors of 4.3 kΩ at each I/O pin. This simplifies

the system implementation and reduces BOM count. Though external pull-up resistors are not

required, they might be added to shorten the rise times of I2C signals even further.

The NCA9700 provides true signal buffering as the device implementation does not use the

pass-FET topology. No static or incremental offsets are needed either, and the lock-free operation

is guaranteed by an innovative implementation of the buffers. The very low VOL levels on port A

and B improve the noise margin in the application and the potential noise components of input

signals are filtered out by Schmitt trigger inputs. To reduce EMI, the negative edges of output

signals are slew-controlled.

The NCA9700 is well suited for high-performance low-power applications which use the I2C

communication protocol.

2. Features and benefits

? Two-channel bidirectional I2C buffer

? Voltage level translation from 1.08 V to 3.6 V at both port A and port B with unconstrained

combination of the supply voltage levels

? Guaranteed 1 MHz operation (true I2C Fast-mode Plus, Fm+)

? Support for the I2C Standard-mode (Sm) and Fast-mode (Fm) operation

? No static voltage offset

? Very low VOL on I/O pins of the port A; VOL regulated to 0.1VCCB on I/O pins of the port B

? Input and output rising-edge signal accelerators at all I/Os

? Active-HIGH enable input referenced to VCCA supply

? Lock-free operation

? Glitch-free and sequence-independent IC power-up

? Open-drain input/outputs

? Series connection and star connection of NCA9700 devices possible

? I2C clock stretching support

? Compatibility with I2C bus and SMBus protocols

? Latch-up performance exceeds 100 mA per JESD 78B Class II

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV

? Very small footprint

3. Applications

? Smart phones and tablets

? Portable medical devices

? Portable instrumentation and test equipment

? Devices for IoT applications

? Power-sensitive applications