NHPXA270中文資料英特爾數(shù)據(jù)手冊PDF規(guī)格書

Introduction

The Intel? PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances in mobile technology over its predecessor, the Intel? PXA255 processor. These same attributes and features also make the PXA270 processor ideal for embedded applications. The PXA270 processor redefines scalability by operating from 104 MHz up to 624 MHz, providing enough performance for the most demanding mobile applications.

■ High-performance processor:

—Intel XScale? microarchitecture with Intel? Wireless MMX? Technology

—7 Stage pipeline

—32 KB instruction cache

—32 KB data cache

—2 KB “mini” data cache

—Extensive data buffering

■ 256 Kbytes of internal SRAM for high speed code or data storage preserved during low-power states

■ High-speed baseband processor interface (Mobile Scalable Link)

■ Rich serial peripheral set:

—AC’97 audio port

—I2S audio port

—USB Client controller

—USB Host controller

—USB On-The-Go controller

—Three high-speed UARTs (two with hardware flow control)

—FIR and SIR infrared communications port

■ Hardware debug features — IEEE JTAG interface with boundary scan

■ Hardware performance-monitoring features with on-chip trace buffer

■ Real-time clock

■ Operating-system timers

■ LCD Controller

■ Universal Subscriber Identity Module interface

■ Low power:

—Wireless Intel Speedstep? Technology

—Less than 500 mW typical internal dissipation

—Supply voltage may be reduced to 0.85 V

—Four low-power modes

—Dynamic voltage and frequency management

■ High-performance memory controller:

—Four banks of SDRAM: up to 104 MHz @ 2.5V, 3.0V, and 3.3V I/O interface

—Six static chip selects

—Support for PCMCIA and Compact Flash

—Companion chip interface

■ Flexible clocking:

—CPU clock from 104 to 624 MHz

—Flexible memory clock ratios

—Frequency changes

—Functional clock gating

■ Additional peripherals for system connectivity:

—SD Card / MMC Controller (with SPI mode support)

—Memory Stick card controller

—Three SSP controllers

—Two I2C controllers

—Four pulse-width modulators (PWMs)

—Keypad interface with both direct and matrix keys support

—Most peripheral pins double as GPIOs