NTE21256中文資料NTE數(shù)據(jù)手冊PDF規(guī)格書

Description:

The NTE21256 is a 262,144 word by 1–bit dynamic Random Access Memory. This 5V–only component is fabricated with N–channel silicon gate technology.

Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard 16–Lead DIP package. Features of this device include single power supply with ±10 tolerance, on–chip address, date registers which eliminate the need for interface registers, and fully TTL compatible inputs and outputs, including clocks.

In addition to the usual read, write, and read–modify–write cycles, the NTE21256 is capable of early and late write cycles, RAS–only refresh, and hidden refresh. Common I/O capability is given by using early write operation.

The NTE21256 also features page mode which allows high–speed random access of bits in the same row.

Features:

? 262,144 x 1–Bit Organization

? Single +5V Supply, ±10 Tolerance

? Low Power Dissipation:

–385mW active (Max)

–28mW standby (Max)

? Access Time: 150ns

? Cycle Time: 260ns

? All Inputs and Outputs TTL Compatible

? On–Chip Substrate Bias Generator

? Three–State Data Output

? Read, Write, Read–Modify–Write, RAS–Only–Refresh, Hidden Refresh

? Common I/O Capability using “Early Write” Operation

? Page Mode Read and Write, Read–Write

? 256 Refresh Cycles with 4ms Refresh Period