OP15AZMDA中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

The ADI-JFET input series of devices offer clear advantages over industry-generic devices and are superior in both cost and performance to many dielectrically-isolated and hybrid op amps. All devices offer offset voltages as low as 0.5 mV with TCVOS guaranteed to 5 μV°C. A unique input bias cancellation circuit reduces the IB by a factor 10 over conventional designs. In addition ADI specifies IB and IOS with the devices warmed up and operating at 25°C ambient.

FEATURES

Significant Performance Advantages over LF155 and

LF157 Devices

Low Input Offset Voltages: 500 V Max

Low Input Offset Voltage Drift: 2.0 V/°C

Minimum Slew Rate Guaranteed on All Models

Temperature-Compensated Input Bias Currents

Bias Current Specified Warmed-Up Over Temperature

Internal Compensation

Low Input Noise Current: 0.01 pA/√Hz

High Common-Mode Rejection Ratio: 100 dB

Models with MIL-STD 883 Processing Available

OP15

156 Speed with 155 Dissipation: 80 mW Typ

Wide Bandwidth: 6 MHz

High Slew Rate: 13 V/μs

Fast Settling to ±0.1: 1,200 ns

OP17

Highest Slew Rate: 60 V/μs

Fastest Settling to ±0.1: 600 ns

Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz

Guaranteed Input Bias Current @ 125°C