ORT82G5集成電路（IC）的FPGA（現(xiàn)場(chǎng)可編程門陣列）規(guī)格書PDF中文資料

Introduction

Agere Systems Inc. has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips (SoC) architecture, the ORT82G5 is made up of backplane transceivers containing eight channels, each operating at up to 3.125 Gbits/s (2.5 Gbits/s data rate), with a fullduplex synchronous interface with built-in clock and data recovery (CDR), along with up to 400k usable FPGA system gates. The CDR circuitry is a macrocell available from Ageres smart silicon macro library, and has already been implemented in numerous applications including ASICs, standard products, and FPSCs to create interfaces for SONET/SDH, STS-48/STM-16, STS-192/STM-64, and 10 Gbit Ethernet applications.