P102-04SC中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書
P102-04SC規(guī)格書詳情
DESCRIPTION
The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
? Frequency range 50 ~ 120MHz.
? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
? Zero input - output delay.
? Less than 700 ps device - device skew.
? Less than 250 ps skew between outputs.
? Less than 200 ps cycle - cycle jitter.
? Output Enable function tri-state outputs.
? 3.3V operation.
? Available in 8-Pin 150mil SOIC.
產(chǎn)品屬性
- 型號(hào)：
P102-04SC
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Low Skew Output Buffer
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SC |
23+ |
NA/ |
302 |
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價(jià) | ||
SC |
24+ |
SOP-8 |
58000 |
全新原廠原裝正品現(xiàn)貨,可提供技術(shù)支持、樣品免費(fèi)! |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
TEPBGA-689 |
6982 |
原廠原裝正品現(xiàn)貨,代理渠道,支持訂貨!!! |
詢價(jià) | ||
ST |
TO-92 |
36900 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價(jià) | |||
尼克森NIKOS |
19+ |
() |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
PHASELINK |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
PHSELINK |
22+ |
SOP8 |
33374 |
原裝正品現(xiàn)貨,可開13個(gè)點(diǎn)稅 |
詢價(jià) | ||
FREESCALE |
24+ |
65200 |
詢價(jià) | ||||
PHASELIN |
23+ |
SOP |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
24+ |
SOP8 |
700 |
詢價(jià) |
