首頁>P2V28S20ATP-7>規(guī)格書詳情
P2V28S20ATP-7中文資料VML數(shù)據(jù)手冊PDF規(guī)格書
P2V28S20ATP-7規(guī)格書詳情
DESCRIPTION P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
FEATURES
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -7:143MHz/-75:133MHz/-8:100MHz
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
產(chǎn)品屬性
- 型號：
P2V28S20ATP-7
- 制造商：
VML
- 制造商全稱：
VML
- 功能描述：
128Mb SDRAM Specification
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
MIRA |
23+ |
60000 |
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種 |
詢價 | |||
MIRA |
NA |
8560 |
一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨 |
詢價 | |||
MIRA |
20+ |
TSOP |
2960 |
誠信交易大量庫存現(xiàn)貨 |
詢價 | ||
MIRA |
2020+ |
TSOP-54 |
80000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
詢價 | ||
MIRA |
23+24 |
TSOP54 |
29650 |
原裝原盤原標,提供BOM一站式配單 |
詢價 | ||
MIRA |
08+ |
TSOP |
386 |
普通 |
詢價 | ||
MIRA |
23+ |
TSOP54 |
1500 |
特價庫存 |
詢價 | ||
MIRA |
2022 |
TSOP-54 |
80000 |
原裝現(xiàn)貨,OEM渠道,歡迎咨詢 |
詢價 | ||
MIRA |
2023+ |
TSOP |
8635 |
全新原裝正品,優(yōu)勢價格 |
詢價 | ||
MIRA |
SOP |
1000 |
正品原裝--自家現(xiàn)貨-實單可談 |
詢價 |
