P80C31SBPN集成電路（IC）的微控制器規(guī)格書PDF中文資料

DESCRIPTION

The Philips 80C31/32 is a high-performance static 80C51 design

fabricated with Philips high-density CMOS technology with operation

from 2.7 V to 5.5 V.

The 80C31/32 ROMless devices contain a 128 × 8 RAM/256 × 8

RAM, 32 I/O lines, three 16-bit counter/timers, a six-source,

four-priority level nested interrupt structure, a serial I/O port for

either multi-processor communications, I/O expansion or full duplex

UART, and on-chip oscillator and clock circuits.

In addition, the device is a low power static design which offers a

wide range of operating frequencies down to zero. Two software

selectable modes of power reduction—idle mode and power-down

mode are available. The idle mode freezes the CPU while allowing

the RAM, timers, serial port, and interrupt system to continue

functioning. The power-down mode saves the RAM contents but

freezes the oscillator, causing all other chip functions to be

inoperative. Since the design is static, the clock can be stopped

without loss of user data and then the execution resumed from the

point the clock was stopped.

FEATURES

? 8051 Central Processing Unit

– 128 × 8 RAM (80C31)

– 256 × 8 RAM (80C32)

– Three 16-bit counter/timers

– Boolean processor

– Full static operation

– Low voltage (2.7 V to 5.5 V@ 16 MHz) operation

? Memory addressing capability

– 64k ROM and 64k RAM

? Power control modes:

– Clock can be stopped and resumed

– Idle mode

– Power-down mode

? CMOS and TTL compatible

? TWO speed ranges at VCC = 5 V

– 0 to 16 MHz

– 0 to 33 MHz

? Three package styles

? Extended temperature ranges

? Dual Data Pointers

? 4 level priority interrupt

? 6 interrupt sources

? Four 8-bit I/O ports

? Full–duplex enhanced UART

– Framing error detection

– Automatic address recognition

? Programmable clock out

? Asynchronous port reset

? Low EMI (inhibit ALE)

? Wake-up from Power Down by an external interrupt