P89LPC9331HDH中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

General description

The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9331/9341/9351/9361 in order to reduce component count, board space, and system cost.

Features and benefits

Principal features

■ 4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 256-byte RAM data memory. P89LPC9351 and P89LPC9361 also include a 512-byte auxiliary on-chip RAM.

■ 512-byte customer data EEPROM on-chip allows serialization of devices, storage of setup parameters, etc. (P89LPC9351/9361)

■ Dual 4-input multiplexed 8-bit ADC/DAC outputs. Two analog comparators with selectable inputs and reference source.

■ Dual Programmable Gain Amplifiers (PGA) with selectable gains of 2x, 4x, 8x, or 16x can be applied to ADCs and analog comparator inputs. (P89LPC9351/9361)

■ On-chip temperature sensor integrated with ADC module.

■ Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output).

■ A 23-bit system timer that can also be used as a real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer.

■ Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port.

■ Capture/Compare Unit (CCU) provides PWM, input capture, and output compare functions. (P89LPC9351/9361)

■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).

■ Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails.

■ 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options.