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PAC25140-T中文資料QORVO數(shù)據(jù)手冊PDF規(guī)格書

PAC25140-T
廠商型號

PAC25140-T

功能描述

10S-20S or 10S-16S Intelligent BMS with Integrated MCU and Cell Balancing

文件大小

2.33144 Mbytes

頁面數(shù)量

88

生產(chǎn)廠商 Qorvo, Inc
企業(yè)簡稱

QORVO

中文名稱

Qorvo, Inc官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-3 17:46:00

PAC25140-T規(guī)格書詳情

Key Features

MCU

? 150MHz Arm? Cortex?-M4F

o 128kB FLASH

o 32kB SRAM with SECDED ECC

o 1kB INFO FLASH for general use

o Floating Point Unit

o 32-bit hardware divider

o Single-cycle 32-bit x 32-bit hardware multiplier

o DSP Instructions and Saturation Arithmetic Support

o 32 interrupts, 8 priority levels

o 8-region Memory Protection Unit (MPU)

o Wake-up Interrupt Controller (WIC) allowing power-saving sleep modes

? Debug

o Single Wire Debug I/F (SWD)

o JTAG programming interface

o Embedded Trace Macrocell (ETM) for in-system debugging at real-time without breakpoints

? Sleep/Deep Sleep & Clock-gating for low-power operation

MCU ADC

? 12-bit resolution

? 2.5MSPS

? Programmable Dynamic Triggering and Sampling Engine (DTSE)

Timing Generators

? Four 16-bit PWM timers with up to 32 PWM/CC blocks

? 24-bit SysTick count-down timer

? 2 x 24-bit General-purpose count-down timers with interrupt

? 2 x Windowed Watch-dog Timer (WWDT) running off independent clock

? Real-time Clock (RTC)

? Wake-up timer for ultra-low power hibernate mode

IO

? 3.3V Digital I/O or Analog Input for ADC

? 24 general-purpose IO with flexible interrupt controller

? Configurable weak pull-up or pull-down

? Configurable drive-strength (6mA to 25mA)

? Flexible peripheral MUX allowing each IO pin to be configured with one of up to 8 peripheral functions

Communication Peripherals

? 3 x USART (Either SPI or UART)

o SPI Master/Slave up to 25 MHz

o UART up to 1Mbps

? I2C/SMBus Master/Slave

? CAN 2.0B Controller

Miscellaneous

? 4-Level User-Configurable Code Protection

? CRC Engine

? 96-bit Unique ID

Power Manager

? Up to 145V supply input Buck DC/DC Controller

o OC, OV and UV protection

? High-Voltage Charge Pump

? 5V/250mA system regulator

? Integrated LDOs for analog, IO, and core supplies

? Power and temperature monitor, warning, and fault detection

? Low-Power Operation

o 3μA total hibernate mode

o Push Button, PACK+/Charger Detect, and Timer wakeup modes

Configurable Analog Front-End (CAFETM)

? Programmable-Gain Differential amplifier and 16-bit Sigma-Delta ADC for battery pack current sense

? 16-bit Sigma-Delta ADC for voltage sense

? Integrated ADC references

? Programmable over-current shutdown

? Power supply monitoring via ADC

? Low-speed independent clock source

Application Specific Power Drivers (ASPDTM)

? Integrated high-side gate drivers for external CHG and DSG FETs

? Integrated low-side gate driver for pack FUSE blow FET

Integrated Cell Balancing

? Cell balancing for up to 20 cells

Packaging

? QFN 10x10mm 68-pin package, 0.5mm pitch

? Exposed pad for thermal management

? TA = -40°C to 105°C

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