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PALCE20V8Q-15JI5中文資料超威半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

PALCE20V8Q-15JI5
廠商型號(hào)

PALCE20V8Q-15JI5

功能描述

EE CMOS 24-Pin Universal Programmable Array Logic

文件大小

235.53 Kbytes

頁(yè)面數(shù)量

16 頁(yè)

生產(chǎn)廠商 Advanced Micro Devices
企業(yè)簡(jiǎn)稱

AMD超威半導(dǎo)體

中文名稱

美國(guó)超威半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-11-19 20:43:00

PALCE20V8Q-15JI5規(guī)格書(shū)詳情

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices.

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all GAL 20V8/As

■ Electrically erasable CMOS technology provides reconfigurable logic and full testability

■ High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

■ Direct plug-in replacement for a wide range of 24-pin PAL devices

■ Programmable enable/disable control

■ Outputs individually programmable as registered or combinatorial

■ Peripheral Component Interconnect (PCI) compliant

■ Preloadable output registers for testability

■ Automatic register reset on power-up

■ Cost-effective 24-pin plastic SKINNYDIP and 28-pin PLCC packages

■ Extensive third-party software and programmer support through FusionPLD partners

■ Fully tested for 100 programming and functional yields and high reliability

■ Programmable output polarity

■ 5-ns version utilizes a split leadframe for improved performance

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