PCA9516APW集成電路（IC）的信號緩沖器、中繼器、分離器規(guī)格書PDF中文資料

General description

The PCA9516A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems.

While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDAn) and the clock (SCLn) lines, thus enabling five buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9516A enables the system designer to divide the bus into five segments off of a hub where any segment-to-segment transition sees only one repeater delay.

Features

■ 5 channel, bidirectional buffer

■ I2C-bus and SMBus compatible

■ Active HIGH individual repeater enable input

■ Open-drain input/outputs

■ Lock-up free operation

■ Supports arbitration and clock stretching across the repeater

■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

■ Powered-off high-impedance I2C-bus pins

■ Operating supply voltage range of 2.3 V to 3.6 V

■ 5.5 V tolerant I2C-bus and enable pins

■ 0 Hz to 400 kHz clock frequency1

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Packages offered: SO16 and TSSOP16