PCA9518集成電路（IC）的專用規(guī)格書PDF中文資料

DESCRIPTION

The PCA9518 is a BiCMOS integrated circuit intended for application in I2C and SMBus systems. While retaining all the operating modes and features of the I2C system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling virtually unlimited buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9518 enables the system designer to divide the bus into an unlimited number of segments off of a hub where any segment to segment transition sees only one repeater delay and is multiple master capable on each segment. Using multiple PCA9518 parts, any width hub (in multiples of five)1 can be implemented using the expansion pins.

A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another PCA9518 cluster.

Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster thanks to the EXPxxxx pins that allow the I2C signals to be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster.

Since there is no direction pin, slightly different “l(fā)egal” low voltage levels are used to avoid lock up conditions between the input and the output of individual repeaters in the cluster. A “regular low” applied at the input of any of the PCA9518 devices will then be propagated as a “buffered low” with a slightly higher value to all enabled outputs in the PCA9518 cluster. When this “buffered low” is applied to a PCA9515 and PCA9516 or separate PCA9518 cluster (not connected via the EXPxxx pins) in series, the second PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a “regular low” and will not propagate it as a “buffered low ” again. The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 but can be used in series with themselves since they use shifting instead of static offsets to avoid lock up conditions.

FEATURES

? Expandable 5 channel, bi-directional buffer

? I2C-bus and SMBus compatible

? Active-HIGH individual repeater enable inputs

? Open-drain input/outputs

? Lock-up free operation

? Supports arbitration and clock stretching across the repeater

? Accommodates standard mode and fast mode I2C devices and multiple masters

? Powered-off high-impedance I2C pins

? Operating supply voltage range of 3.0 V to 3.6 V

? 5 V tolerant I2C and enable pins

? 0 kHz to 400 kHz clock frequency2

? ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101.

? Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA.

? Package offerings: SO and TSSOP