PCA9665集成電路（IC）的控制器規(guī)格書PDF中文資料

General description

The PCA9665/PCA9665A serves as an interface between most standard parallel-bus

microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

system to communicate bidirectionally with the I2C-bus. The PCA9665/PCA9665A can

operate as a master or a slave and can be a transmitter or receiver. Communication with

the I2C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake.

The PCA9665/PCA9665A controls all the I2C-bus specific sequences, protocol, arbitration

and timing with no external timing element required.

The PCA9665 and PCA9665A have the same footprint as the PCA9564 with additional

features:

? 1 MHz transmission speeds

? Up to 25 mA drive capability on SCL/SDA

? 68-byte buffer

? I2C-bus General Call

? Software reset on the parallel bus

Features and benefits

? Parallel-bus to I2C-bus protocol converter and interface

? Both master and slave functions

? Multi-master capability

? Internal oscillator trimmed to 15 accuracy reduces external components

? 1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability

? I2C-bus General Call capability

? Software reset on parallel bus

? 68-byte data buffer

? Operating supply voltage: 2.3 V to 3.6 V

? 5 V tolerant I/Os

? Standard-mode and Fast-mode I2C-bus capable and compatible with SMBus

? PCA9665A ‘glitch-free’ restart is suitable for use with buffer drivers

? ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

? Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

? Packages offered:

? PCA9665: SO20, TSSOP20, HVQFN20

? PCA9665A: TSSOP20