PCK2509SLDH中文資料飛利浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2509SL operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

FEATURES

? Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications

? When outputs are disabled, the PLL and feedback output are disabled, dropping AICC to 100 μA in stand-by mode when input clock signal is present.

? See PCK2509SA for JEDEC compliant option where PLL remains locked when outputs are disabled.

? Spread Spectrum clock compatible

? Operating frequency 50 to 150 MHz

? (tphase error – jitter) at 100 to133 MHz = ±50 ps

? Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps

? Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps

? Pin-to-pin skew < 200 ps

? Available in plastic 24-Pin TSSOP

? Distributes one clock input to one bank of five outputs and one bank of four outputs

? External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input

? On-Chip series damping resistors

? No external RC network required

? Operates at 3.3 V

? Inputs compatible with 2.5 V and 3.3 V ranges

? See page 7 for Characteristic curves.