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PDSP16318A中文資料ZARLINK數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
PDSP16318A規(guī)格書(shū)詳情
The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications.
Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete arithmetic solution for a Radix 2 DIT FFT Butterfly. A new complex Butterfly result can be generated every 100ns allowing 1k complex FTTs to to be executed in 512μs.
FEATURES
■ Full 10MHz Throughout in FFT Applications
■ Four Independent 16-bit I/O Ports
■ 20-bit Addition or Accumulation
■ Fully Compatible with PDSP16112 Complex Multiplier
■ On Chip Shift Structures for Result Scaling
■ Overflow Detection
■ Independent Three-State Outputs and Clock Enables for 2 Port 10MHz Operation
■ 1.4 micron CMOS
■ 500mW Maximum Power Dissipation
■ 100 pin ceramic QFP
產(chǎn)品屬性
- 型號(hào)：
PDSP16318A
- 制造商：
ZARLINK
- 制造商全稱(chēng)：
Zarlink Semiconductor Inc
- 功能描述：
Complex Accumulator
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|---|---|---|---|---|---|---|---|
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25 |
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64 |
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10+ |
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54 |
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詢(xún)價(jià) | |||
18 |
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200 |
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詢(xún)價(jià) | |||
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2318+ |
PGA |
4862 |
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詢(xún)價(jià) | ||
ZARLINK |
23+ |
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10000 |
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21+ |
PGA |
645 |
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詢(xún)價(jià) |
