PEF20571中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書
PEF20571規(guī)格書詳情
Addendum to “DELIC Clock System Synchronization”
The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1).
As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet the following describes the system behaviour when using the VIP PEB 20590 or PEB 20591 in LT-T mode, for example when synchronizing to the Central Office.
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference signal is generated and used as input signal for the DELIC DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO phase detector (PD). The second input to PD is another 8 kHz signal which originates from the 16.384 MHz output of the DCXO.
The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider generates the 15.36 MHz layer 1 clock which is used to clock the VIP.
產(chǎn)品屬性
- 型號：
PEF20571
- 制造商：
INFINEON
- 制造商全稱：
Infineon Technologies AG
- 功能描述：
DSP Embedded Line and Port Interface Controller
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
INFINEON/英飛凌 |
QFP |
98900 |
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詢價(jià) | |||
INTEL/英特爾 |
20+ |
SMD |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
24+ |
3000 |
公司存貨 |
詢價(jià) | ||||
INFINEON |
16+ |
QFP |
2500 |
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢! |
詢價(jià) | ||
INFINEON |
23+ |
7000 |
詢價(jià) | ||||
INTEL/英特爾 |
2021+ |
SMD |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價(jià) | ||
英飛凌 |
22+ |
NA |
500000 |
萬三科技,秉承原裝,購芯無憂 |
詢價(jià) | ||
INTEL |
2022+ |
原廠原包裝 |
8600 |
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詢價(jià) | ||
INFINEON |
1923+ |
BGAQFP |
488 |
原盒原包裝只有原裝假一罰十價(jià)優(yōu)! |
詢價(jià) | ||
INFINEON |
525 |
TQFP100 |
3 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) |
