PGD3162AM550EK中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General description

The GD3162 is an advanced, galvanically isolated, single-channel gate driver designed

to drive the latest SiC and IGBT modules for xEV traction inverters. The device does this

while enabling space savings and performance improvements through advanced gatedrive

functionality.

The GD3162 offers integrated galvanic isolation, a programmable interface via SPI, and

advanced programmable protection features, such as overtemperature, desaturation,

and current sense protection. GD3162 with integrated boost capability, can drive most

SiC MOSFET and IGBT/SiC module gates directly and is able to shape the gate drive

capability in order to improve the power device’s switching performance and reduce

voltage stress.

The control of the gate strength can be done using either SPI commands or the GS

Enable Pins. GS_ENH logic controls the drive strength of the turn on, and GS_ENL

controls the drive strength of the turn off. To further improve performance, these functions

are designed to operate independent of each other. Three separate pullup drive strengths

and three pulldown drive strengths are made available via trilevel functions on the input

pins or commands in SPI.

The GD3162 autonomously manages faults and reports power device and gate driver

status via the INTB pin. VCE/VDS monitoring, as well as VGE monitoring, can be

selected to be output on the INTA/RTRPT pin.

The GD3162 includes self-test and control protection functions for design of high

functional safety integrity level systems (ASIL C/D) and meets the stringent requirements

of automotive applications, being fully AEC-Q100 grade 1 qualified.

Features and benefits

This section summarizes the key features, safety features, and regulatory approvals for

the GD3162.

2.1 Key features

? Integrated galvanic signal isolation (up to 8 kV)

? Integrated boost capability for increased drive strength: Up to 10 A/ 20 A/ 30 A source/

sink current available by gate strength selection

? SPI or 3-state enabled GS_ENH and GS_ENL low-voltage domain pins to dynamically

control gate drive strength. Adjustment of gate strength up to 20 KHz supported

? Dual gate pullup pins and dual gate pulldown pins for enhanced drive capability,

synchronous adjustment of gate strength, reduced thermal loading during weak drive,

and independent verification of each drive state operation

? SPI programmable ISEN/COMP setpoint, to allow the gate driver to automatically

control gate drive strength based on high-voltage domain inputs.

? Temperature sense pins compatible with NTC and PTC thermistors allow for local

control of temperature based gate-drive strength, as well as power device temperature

monitoring via AOUT pin or SPI.

? Programmable ADC delay – Up to 8 μs sampling delay from rising or falling edge of

PWM.

? Active Bus Discharge Functionality (PGD3162AM551EK and PGD3162AM581EK only)

– Provides either MCU controlled or Safety Logic Controlled Gate drive to actively

discharge the DC Link Capacitor.

? SPI interface for safety monitoring, configuration, and diagnostic reporting

? VCE power device monitoring via the low-voltage domain INTA/RTRPT pin

? Supports high PWM switching frequencies: PWM up to 100 kHz, thermally limited

? Fail-safe state management from LV and HV domain for user-selectable safe state

? Configurable desaturation and current sense optimized for protecting SiC and IGBTs

against short circuit in less than 1 μs

? INTA/RTRPT and INTB Interrupt pins for current and voltage Fault Reporting and, if

selected, VCE or VGE real-time reporting.

? Advanced two-level turn-off (2LTO) in combination with soft shut down gate current to

reduce current and voltage stress associated with rapid turnoff.

? CMTI > 100 V/ns

2.2 Safety features

? Certified compliant with ISO 26262, supporting ASIL D level functional safety

? Error checking of SPI and configuration data with 8-bit CRC

? Autonomously manages severe faults and reports status via configurable INTB and/or

INTA/RTRPT pins, and SPI interface

? VCE/VGE real-time cycle-by-cycle monitoring and reporting for feedback of power

device status.

? Built-in self-test (BIST) of all analog and digital circuits

? Continuous watchdog of communications across isolation barrier

? Deadtime enforcement

? Overvoltage and undervoltage supervision of 5 V bias supply for LV circuitry

? Overvoltage and undervoltage supervision of VCC supply for HV circuitry

? Dedicated fail-safe state management pins on both low-voltage and high-voltage sides

2.3 Safety and regulatory approvals

? Reinforced isolation per DIN V VDE V 0884-10

? Withstand 5000 V rms (1 minute) isolation per UL 1577

? AEC-Q100 grade 1 automotive qualified