PI6C102中文資料百利通數(shù)據(jù)手冊PDF規(guī)格書

Description

The PI6C102 is a high-speed low-noise clock generator designed to work with the Pericom’s PI6C18x clock buffer to meet all clock needs for Mobile Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported.

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required.

An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system.

Features

? Two copies of CPU clock with VDD of 2.5V ±5

? 100 MHz or 66.6 MHz operation

? Six copies of PCI clock, (synchronous with CPU clock) 3.3V

? One copy of Ref. Clock @ 14.31818 MHz (3.3VTTL)

? Low cost 14.31818 MHz crystal oscillator input

? Power management control

? Isolated core VDD, VSS pins for noise reduction

? 28-pin SSOP package (H)