PI6C2510-133E集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Description

The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable.

This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.

Features

? Operating Frequency up to 150 MHz

? Low-Noise Phase-Locked Loop Clock Distribution that

meets 133 MHz Registered DIMM Synchronous DRAM modules

for server/workstation/PC applications

? Allows Clock Input to have Spread Spectrum modulation

for EMI reduction

? Low jitter: Cycle-to-Cycle jitter ±75ps max.

? On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

? Operates at 3.3V VCC, 0–85°C

? Packages (Pb-free & Green available):

– Plastic 24-pin TSSOP (L)