首頁(yè)>PIC18F25Q43T-I/SS>規(guī)格書(shū)詳情
PIC18F25Q43T-I/SS中文資料微芯科技數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
PIC18F25Q43T-I/SS |
功能描述 | 28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology |
文件大小 |
12.12637 Mbytes |
頁(yè)面數(shù)量 |
950 頁(yè) |
生產(chǎn)廠商 | Microchip Technology |
企業(yè)簡(jiǎn)稱 |
Microchip【微芯科技】 |
中文名稱 | 微芯科技股份有限公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-7 23:00:00 |
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PIC18F25Q43T-I/SS規(guī)格書(shū)詳情
The PIC18-Q43 microcontroller family is available in 28/40/44/48-pin devices for real-time control applications.
This family features a 12-bit Analog-to-Digital Converter with Computation (ADCC) automating Capacitive Voltage
Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold
comparison. This family showcases a new 16-bit Pulse-Width Modulator (PWM) module which provides dual
independent outputs on the same time base. Additional features include vectored interrupt controller with
fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, Universal
Asynchronous Receiver-Transmitter (UART) with support for asynchronous, Digital Multiplex (DMX), Digital
Addressable Lighting Interface (DALI) and Local Interconnect Network (LIN) protocols, Serial Peripheral Interface
(SPI), I2C, memory features like Memory Access Partition (MAP) to support users in data protection and bootloader
applications, and Device Information Area (DIA), which stores factory calibration values to help improve temperature
sensor accuracy.
Features
? C Compiler Optimized RISC Architecture
? Operating Speed:
– DC – 64 MHz clock input
– 62.5 ns minimum instruction cycle
? Six Direct Memory Access (DMA) Controllers:
– Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR
spaces
– User programmable source and destination sizes
– Hardware and software triggered data transfers
? Vectored Interrupt Capability:
– Selectable high/low priority
– Fixed interrupt latency of three instruction cycles
– Programmable vector table base address
– Backwards compatible with previous interrupt capabilities
? 127-Level Deep Hardware Stack
? Low-Current Power-on Reset (POR)
? Configurable Power-up Timer (PWRT)
? Brown-out Reset (BOR)
? Low-Power BOR (LPBOR) Option
? Windowed Watchdog Timer (WWDT):
– Watchdog Reset on too long or too short interval between watchdog clear events
– Variable prescaler selection
– Variable window size selection
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28SOIC |
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SOIC-28 |
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TO-18 |
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