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PIMXRT1041CJM4A中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
PIMXRT1041CJM4A |
功能描述 | i.MX RT1050 Crossover Processors Data Sheet for Industrial Products |
文件大小 |
1.2613 Mbytes |
頁(yè)面數(shù)量 |
115 頁(yè) |
生產(chǎn)廠商 | NXP Semiconductors |
企業(yè)簡(jiǎn)稱 |
nxp【恩智浦】 |
中文名稱 | 恩智浦半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-16 20:00:00 |
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Features
The i.MX RT1050 processors are based on Arm Cortex-M7 Core? Platform, which has the following
features:
? Supports single Arm Cortex-M7 Core with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
? Integrated MPU, up to 16 individual protection regions
? Up to 512 KB I-TCM and D-TCM in total
? Frequency of 528 MHz
? Cortex M7 CoreSight? components integration for debug
? Frequency of the core, as per Table 10, Operating ranges, on page 21.
The SoC-level memory system consists of the following additional components:
— Boot ROM (96 KB)
— On-chip RAM (512 KB)
– Configurable RAM size up to 512 KB shared with M7 TCM
? External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR/NAND FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
? Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
— Four Periodical Interrupt Timer (PIT)
– Generic 16-bit resolution timer
– Periodical interrupt generation
— Four Quad Timers (QTimer)
– 4-channel generic 16-bit resolution timer for each
– Each support standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels for each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Encoder/Decoders
Each i.MX RT1050 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
? Display Interface:
— Parallel RGB LCD interface
– Support 8/16/24 bit interface
– Support up to 1366 x 768 WXGA resolution
– Support Index color with 256 entry x 24 bit color LUT
– Smart LCD display with 8/16-bit MPU/8080 interface
? Audio:
— S/PDIF input and output
— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
? Generic 2D graphics engine:
— BitBlit
— Flexible image composition options—alpha, chroma key
— Image rotation (90?, 180?, 270?)
— Porter-Daff operation
— Image size
— Color space conversion
— Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
— Standard 2D-DMA operation
? Camera sensors:
— Support 24-bit, 16-bit, and 8-bit CSI input
? Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– MMC 4.5 compliance with HS200 support up to 200 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
— One 10/100 M Ethernet controller with support for IEEE1588
— Eight universal asynchronous receiver/transmitter (UARTs) modules
— Four I2C modules
— Four SPI modules
— Two FlexCAN modules
? GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— Two FlexIOs
The i.MX RT1050 processors integrate advanced power management unit and controllers:
? Full PMIC integration. On-chip DCDC and LDO
? Temperature sensor with programmable trip points
? GPC hardware power management controller
The i.MX RT1050 processors support the following system debug:
? Arm CoreSight debug and trace architecture
? Trace Port Interface Unit (TPIU) to support off-chip real-time trace
? Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse
Security functions are enabled and accelerated by the following hardware:
? High Assurance Boot (HAB)
? Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
? Bus Encryption Engine (BEE)
— AES-128, ECB, and CTR mode
— On-the-fly QSPI Flash decryption
? True random number generation (TRNG)
? Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
— Zero Master Key (ZMK)
? Secure JTAG Controller (SJC)
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
NEXPERIA/安世 |
23+ |
TSOP-6 |
54258 |
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詢價(jià) | ||
原裝PHILIPS |
21+ |
SOT-163 |
35200 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) | ||
NEXPERIA/安世 |
24+ |
NA |
21000 |
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詢價(jià) | ||
NEXPERIA/安世 |
24+ |
SOT457 |
860000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
NEXPERIA/安世 |
SOT23-6 |
90000 |
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詢價(jià) | |||
NEXPERIA/安世 |
22+ |
SOT457 |
50000 |
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NXP |
21+ |
25000 |
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詢價(jià) | |||
PHILIPS |
22+ |
SOT-163 |
32813 |
原裝正品現(xiàn)貨 |
詢價(jià) | ||
PHILIPS |
9856 |
SOT-163 |
1812 |
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詢價(jià) | ||
NEXPERIA/安世 |
22+ |
SOT457 |
94832 |
鄭重承諾只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) |