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PKD01EY中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

PKD01EY
廠商型號

PKD01EY

功能描述

Monolithic Peak Detector with Reset-and-Hold Mode

文件大小

402.93 Kbytes

頁面數(shù)量

18

生產(chǎn)廠商 Analog Devices
企業(yè)簡稱

AD亞德諾

中文名稱

亞德諾半導(dǎo)體技術(shù)有限公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-22 22:30:00

PKD01EY規(guī)格書詳情

GENERAL DESCRIPTION

The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals.

FEATURES

Monolithic Design for Reliability and Low Cost

High Slew Rate: 0.5 V/μs

Low Droop Rate

TA = 25°C: 0.1 mV/ms

TA = 125°C: 10 mV/ms

Low Zero-Scale Error: 4 mV

Digitally Selected Hold and Reset Modes

Reset to Positive or Negative Voltage Levels

Logic Signals TTL and CMOS Compatible

Uncommitted Comparator On-Chip

Available in Die Form

產(chǎn)品屬性

  • 型號:

    PKD01EY

  • 制造商:

    Analog Devices

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