PL133-67OI集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器規(guī)格書PDF中文資料

PL133-67OI屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由微芯科技股份有限公司制造生產(chǎn)的PL133-67OI時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

General Description

The PL133-67 is an advanced fanout buffer design for

high performance, low-power, small form factor

applications. The PL133-67 accepts a reference clock

input from DC to 150 MHz and provides six outputs of

the same frequency.

The PL133-67 is offered in a TSSOP-16L package and

it offers the best phase noise, additive jitter

performance, and lowest power consumption of any

comparable IC.

The PL133-67 outputs can be disabled to a high

impedance (tri-state) by pulling low the OE pin. When

the OE pin is high, the outputs are enabled and follow

the REF input signal. When the OE pin is left open, a

pull-up resistor on the chip will default the OE pin to

logic 1 so the outputs are enabled.

Features

? 1:6 LVCMOS Output Fanout Buffer from DC

to150 MHz

? Low Additive Phase Jitter of 60 fs RMS

? 8 mA Output Drive Strength

? Low Power Consumption for Portable

Applications

? Low Input-Output Delay

? Output-Output Skew <250 ps

? 2.5V to 3.3V, ±10 Operation

? 1.8V +10/–5 Operation up to 67 MHz

? Operating Temperature Range:

- Commercial: 0°C to +70°C

- Industrial: –40°C to +85°C

? Available in 16-Pin TSSOP Package