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PLL102-03SC中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

PLL102-03SC
廠商型號(hào)

PLL102-03SC

功能描述

Low Skew Output Buffer

文件大小

206.13 Kbytes

頁(yè)面數(shù)量

6 頁(yè)

生產(chǎn)廠商 PhaseLink Corporation
企業(yè)簡(jiǎn)稱(chēng)

PLL

中文名稱(chēng)

PhaseLink Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-12-25 22:30:00

PLL102-03SC規(guī)格書(shū)詳情

DESCRIPTION

The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.

FEATURES

? Frequency range 75 ~ 180MHz.

? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).

? Zero input - output delay.

? Less than 700 ps device - device skew.

? Less than 250 ps skew between outputs.

? Less than 150 ps cycle - cycle jitter.

? Output Enable function tri-state outputs.

? 3.3V operation.

? Available in 8-Pin 150mil SOIC GREEN package.

產(chǎn)品屬性

  • 型號(hào):

    PLL102-03SC

  • 制造商:

    PLL

  • 制造商全稱(chēng):

    PLL

  • 功能描述:

    Low Skew Output Buffer

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2020+
SOP8
8000
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PHASELINK
2016+
SOP8
2500
只做原裝,假一罰十,公司可開(kāi)17%增值稅發(fā)票!
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PHASELINK
23+
NA/
1628
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Phaselink
589220
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PHASELINK
1948+
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6852
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PhaseLink
24+
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3629
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PLL
23+
SOP
9365
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