首頁(yè)>PLL103-07>規(guī)格書(shū)詳情

PLL103-07中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

PLL103-07
廠商型號(hào)

PLL103-07

功能描述

2 DIMM DDR Fanout Buffer

文件大小

144.26 Kbytes

頁(yè)面數(shù)量

7 頁(yè)

生產(chǎn)廠商 PhaseLink Corporation
企業(yè)簡(jiǎn)稱

PLL

中文名稱

PhaseLink Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2024-12-27 13:00:00

PLL103-07規(guī)格書(shū)詳情

DESCRIPTIONS

The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset.

FEATURES

? Generates 12-output buffers from one input.

? Supports VIA Pro266 DDR chipset.

? Supports up to 2 DDR DIMMS.

? Supports up to 400MHz DDR, SDRAMS.

? One additional output for feedback.

? 6 differential clock distribution.

? Less than 5ns delay.

? Skew between any outputs is less than 100 ps.

? 2.5V Supply range.

? Available in 28-pin SSOP.

產(chǎn)品屬性

  • 型號(hào):

    PLL103-07

  • 制造商:

    PLL

  • 制造商全稱:

    PLL

  • 功能描述:

    2 DIMM DDR Fanout Buffer

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
PHASELINK
23+
SOP-8
50000
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Phaseli
2020+
SOP8
8000
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PHASELINK
23+
SOP
360000
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PHASELINK
23+
NA/
3676
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PHASELINK
14+
SOP-8
20
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0603
56930
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PHASELINK
23+
SOP8
50000
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PHASELI
2021+
SOP8
100500
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PHASELINK
24+
SSOP
2987
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Phaselink
SOP8
699839
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