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PLL130-68中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書

PLL130-68
廠商型號

PLL130-68

功能描述

High Speed Translator Buffers: Single ended to PECL or LVDS

文件大小

224.71 Kbytes

頁面數(shù)量

5

生產(chǎn)廠商 PhaseLink Corporation
企業(yè)簡稱

PLL

中文名稱

PhaseLink Corporation官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時(shí)間

2025-1-27 23:00:00

PLL130-68規(guī)格書詳情

DESCRIPTION

The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential out puts (PECL for PLL130-68 or LVDS for PLL130-69). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or

PECL.

FEATURES

? Differential PECL (PLL130-68) or LVDS(PLL130-69) output.

? Accepts any single-ended REFIN input (with as low as 100mV swing).

? Internal AC coupling of REFIN

? Input range from 1.0MHz to 1.0 GHz.

? No Vref required.

? No external current source required.

? 2.5 to 3.3V operation.

? Available in 3x3mm QFN.

產(chǎn)品屬性

  • 型號:

    PLL130-68

  • 制造商:

    PLL

  • 制造商全稱:

    PLL

  • 功能描述:

    High Speed Translator

  • Buffers:

    Single ended to PECL or LVDS

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原裝正品
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