PM73123中文資料PMC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also provides a software device driver for the AAL1gator-8 device.

FEATURES

The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also provides a software device driver for the AAL1gator-8 device.

? Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1

? Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA- 0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis.

? Supports non-DBCES idle channel detection by activating a queue when any of its constituent time slots are active, and deactivating a queue when all of its constituent time slots are inactive.

? Provides AAL1 segmentation and reassembly of 8 individual E1 or T1 lines, 2 H-MVIP lines at 8 MHz, or 1 E3 or DS3 or STS-1 unstructured line.

? Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. Only Cell Level Handshaking is supported. The following modes are supported:

? 8/16-bit Level 2, Multi-Phy Mode (MPHY)

? 8/16-bit Level 1, SPHY

? 8-bit Level 1, ATM Master

? Provides an optional 8/16-bit Any-PHY slave interface.

? Supports up to 256 Virtual Channels (VC).

? Supports n x 64 (consecutive channels) and m x 64 (non-consecutive channels) structured data format.

? Provides transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS). Provides for termination of CAS signaling.

? Allows the CAS nibble to be coincident with either the first or second nibble of the data.

? Provides per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Data and signaling conditioning can be individually enabled. Includes DS3 AIS conditioning support in both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern or old data. Conditioning automatically occurs on underruns.

? In Cell Transmit direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, data and signaling conditioning, ATM Cell header definition. Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported.

? In Cell Transmit direction provides counters for:

? Conditioned cells transmitted for each queue

? Cells which were suppressed for each queue

? Total number of cells transmitted for each queue

? In Cell Receive direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1.

APPLICATIONS

? Multi-service ATM Switch

? ATM Access Concentrator

? Digital Cross Connect

? Computer Telephony Chassis with ATM infrastructure

? Wireless Local Loop Back Haul

? ATM Passive Optical Network Equipment