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PSD814F3A-20MT中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
PSD814F3A-20MT |
功能描述 | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
文件大小 |
1.18057 Mbytes |
頁(yè)面數(shù)量 |
103 頁(yè) |
生產(chǎn)廠商 | STMicroelectronics |
企業(yè)簡(jiǎn)稱 |
STMICROELECTRONICS【意法半導(dǎo)體】 |
中文名稱 | 意法半導(dǎo)體(ST)集團(tuán)官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-18 9:30:00 |
PSD814F3A-20MT規(guī)格書(shū)詳情
Summary description
The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings in-system-programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.
Features
■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs
■ Dual bank Flash memories
– Up to 2 Mbit of primary Flash memory (8 uniform sectors, 32K x8)
– Up to 256 Kbit secondary Flash memory (4 uniform sectors)
– Concurrent operation: read from one memory while erasing and writing the other
■ Up to 256 Kbit SRAM
■ 27 reconfigurable I/Oports
■ Enhanced JTAG serial port
■ PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select decoding
■ 27 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as open-drain outputs.
■ In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows full-chip in-system programmability
– Efficient manufacturing allow easy product testing and programming
– Use low cost FlashLINK cable with PC
■ Page register
– Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ Packages are ECOPACK?
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module |
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詢價(jià) |