PSN74LV595ABQBR中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? 2-V to 5.5-V VCC Operation

? Max tpd of 7.1 ns at 5 V

? Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

? Typical VOHV (Output VOH Undershoot)

> 2.3 V at VCC = 3.3 V, TA = 25°C

? Support Mixed-Mode Voltage Operation on All

Ports

? 8-Bit Serial-In, Parallel-Out Shift

? Ioff Supports Live Insertion, Partial Power-Down

Mode, and Back-Drive Protection

? Shift Register Has Direct Clear

? Latch-Up Performance Exceeds 250 mA Per JESD

17

2 Applications

? Output expansion

? LED matrix control

? 7-segment display control

3 Description

The SN74LV595A device contains an 8-bit serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. Both the shift register clock (SRCLK)

and storage register clock (RCLK) are positive-edge

triggered.