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R5F51306BDFL中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

R5F51306BDFL
廠商型號

R5F51306BDFL

功能描述

32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory, up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply

文件大小

2.48612 Mbytes

頁面數(shù)量

134

生產廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-11-19 17:12:00

R5F51306BDFL規(guī)格書詳情

Features

■ 32-bit RX CPU core

? Max. operating frequency: 32 MHz

Capable of 50 DMIPS in operation at 32 MHz

? Accumulator handles 64-bit results (for a single instruction) from

32-bit × 32-bit operations

? Multiplication and division unit handles 32-bit × 32-bit operations

(multiplication instructions take one CPU clock cycle)

? Fast interrupt

? CISC Harvard architecture with 5-stage pipeline

? Variable-length instructions, ultra-compact code

? On-chip debugging circuit

■ Low power design and architecture

? Operation from a single 1.8-V to 5.5-V supply

? Three low power consumption modes

? Low power timer (LPT) that operates during the software standby state

? Supply current

High-speed operating mode: 96 μA/MHz

Supply current in software standby mode: 0.37 μA

? Recovery time from software standby mode: 4.8 μs

■ On-chip flash memory for code, no wait states

? 64 K/128 K/256 K/383 K/512 Kbytes

? Operation at 32 MHz, read cycle of 31.25 ns

? No wait states for reading at full CPU speed

? Programmable at 1.8 V

? For instructions and operands

■ On-chip data flash memory

? 8 Kbytes (1,000,000 program/erase cycles (typ.))

? BGO (Background Operation)

■ On-chip SRAM, no wait states

? 10 K/16 K/32 K/48 Kbytes size capacities

■ DTC

? Four transfer modes

? Transfer can be set for each interrupt source.

■ ELC

? Module operation can be initiated by event signals without using

interrupts.

? Linked operation between modules is possible while the CPU is sleeping.

■ Reset and supply management

? Eight types of reset, including the power-on reset (POR)

? Low voltage detection (LVD) with voltage settings

■ Clock functions

? External clock input frequency: Up to 20 MHz

? Main clock oscillator frequency: 1 to 20 MHz

? Sub clock oscillator frequency: 32.768 kHz

? PLL circuit input: 4 MHz to 8 MHz

? Low-speed on-chip oscillator: 4 MHz

? High-speed on-chip oscillator: 32 MHz ± 1

? IWDT-dedicated on-chip oscillator: 15 kHz

? Generate a 32.768 kHz clock for the real-time clock

? On-chip clock frequency accuracy measurement circuit (CAC)

■ Realtime clock

? Adjustment functions (30 seconds, leap year, and error)

? Calendar count mode or binary count mode selectable

■ Independent watchdog timer

? 15-kHz on-chip oscillator produces a dedicated clock signal to drive

IWDT operation.

■ Useful functions for IEC60730 compliance

? Self-diagnostic and disconnection-detection assistance functions for

the A/D converter, clock frequency accuracy measurement circuit,

independent watchdog timer, RAM test assistance functions using the

DOC, etc.

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