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R5F521A7BDFM中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

R5F521A7BDFM
廠商型號(hào)

R5F521A7BDFM

功能描述

50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ΔΣ A/D Converter up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC, MPC, RTC; up to 9 comms interfaces

文件大小

2.0083 Mbytes

頁(yè)面數(shù)量

132 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-20 16:32:00

R5F521A7BDFM規(guī)格書(shū)詳情

■ 32-bit RX CPU core

? Max. operating frequency: 50 MHz

Capable of 78 DMIPS in operation at 50 MHz

? Accumulator handles 64-bit results (for a single

instruction) from 32- × 32-bit operations

? Multiplication and division unit handles 32- × 32-bit

operations (multiplication instructions take one CPU

clock cycle)

? Fast interrupt

? CISC Harvard architecture with 5-stage pipeline

? Variable-length instructions, ultra-compact code

? Memory protection unit

? On-chip debugging circuit

■ Low power design and architecture

? Operation from a single 1.8-V to 3.6-V supply

(2.7 V to 3.6 V for the ΔΣ A/D converter operating

voltage)

? Deep software standby mode with RTC remaining usable

? Four low power modes

■ 24-bit ΔΣ A/D Converter

? SNDR = 85dB

? Seven ΔΣ converter units available. Seven channels can

be operated simultaneously or independently.

? Up to x 64 PGA gain for differential input

■ On-chip flash memory for code, no wait states

? 50-MHz operation, 20-ns read cycle

? No wait states for reading at full CPU speed

? 256-K to 512-Kbyte capacities

? User code programmable via the SCI

? Programmable at 1.8 V

? For instructions and operands

■ On-chip data flash memory

? 8 Kbytes

(Number of times of reprogramming: 100,000)

? Erasing and programming impose no load on the CPU.

■ On-chip SRAM, no wait states

? 32-K to 64-Kbyte size capacities

■ DMA

? DMAC: Incorporates four channels

? DTC: Four transfer modes

■ Reset and supply management

? Nine types of reset, including the power-on reset (POR)

? Low voltage detection (LVD) with voltage settings

■ Clock functions

? Frequency of external clock: Up to 20 MHz

? Frequency of the oscillator for sub-clock generation:

32.768 kHz

? PLL circuit input: 4 MHz to 12.5 MHz

? On-chip low- and high-speed oscillators, dedicated onchip

low-speed oscillator for the IWDT

? Generation of a dedicated 32.768-kHz clock for the RTC

? Clock frequency accuracy measurement circuit (CAC)

■ Real-time clock

? Adjustment functions (30 seconds, leap year, and error)

? Year and month display or 32-bit second display (binary

counter) is selectable

? Time capture on event-signal input through external pins

? RTC capable of initiating return from deep software

standby mode

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