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R5F523E6SGNF中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
R5F523E6SGNF |
功能描述 | 32-MHz, 32-bit RX MCUs with up to 256-KB flash memory 2 low-noise and low-drift 24-bit delta-sigma A/D converters, rail-to-rail programmable gain instrumentation amplifiers, a low-drift voltage reference, and on-chip excitation current sources |
文件大小 |
1.3295 Mbytes |
頁(yè)面數(shù)量 |
99 頁(yè) |
生產(chǎn)廠商 | Renesas Technology Corp |
企業(yè)簡(jiǎn)稱 |
RENESAS【瑞薩】 |
中文名稱 | 瑞薩科技有限公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-19 11:08:00 |
R5F523E6SGNF規(guī)格書(shū)詳情
■ 32-bit RXv2 CPU core
? Max. operating frequency: 32 MHz
Capable of 64 DMIPS in operation at 32 MHz
? Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiplysubtract
instructions supported
? Built-in FPU: 32-bit single-precision floating point (compliant to
IEEE754)
? Divider (fastest instruction execution takes two CPU clock cycles)
? Fast interrupt
? CISC Harvard architecture with 5-stage pipeline
? Variable-length instructions, ultra-compact code
? On-chip debugging circuit
? Memory protection unit (MPU) supported
■ Low power design and architecture
? Operation from a single 1.8-V to 5.5-V supply
? Three low power consumption modes
? Low power timer (LPT) that operates during the software standby state
■ On-chip flash memory for code
? Read cycle of 31.25 ns in 32-MHz operation
? No waiting time when the CPU is reading at full speed
? 128-Kbyte to 256-Kbyte capacities
? On-board or off-board user programming
? Programmable at 1.8 V
? For instructions and operands
■ On-chip data flash memory
? 8 Kbytes (1,000,000 program/erase cycles (typ.))
? BGO (Background Operation)
■ On-chip SRAM, no wait states
? 16- to 32-Kbyte size capacities
■ Data transfer functions
? DMAC: Incorporates four channels
? DTC: Four transfer modes
■ ELC
? Module operation can be initiated by event signals without using
interrupts.
? Linked operation between modules is possible while the CPU is
sleeping.
■ Reset and supply management
? Seven types of reset, including the power-on reset (POR)
? Low voltage detection (LVD) with voltage settings
■ Clock functions
? Main clock oscillator frequency: 1 MHz to 20 MHz
? External clock input frequency: Up to 20 MHz
? PLL circuit input: 4 MHz to 8 MHz
? On-chip low- and high-speed oscillators, dedicated on-chip low-speed
oscillator for the IWDT
? Clock frequency accuracy measurement circuit (CAC)
■ Independent watchdog timer
? 15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ Useful functions for IEC60730 compliance
? Self-diagnostic and disconnect detection assistance functions for the A/
D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
■ MPC
? Input/output functions selectable from multiple pins
■ Up to eight communication functions
? CAN (one channel) compliant to ISO11898-1:
Transfer at up to 1 Mbps
? SCI with many useful functions (up to four channels),
asynchronous mode, clock synchronous mode, smart card interface,
reduction of errors in communications using the bit rate modulation
function
? I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
? RSPI (one channel): Transfer at up to 16 Mbps
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