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R5F56604DDFB中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

R5F56604DDFB
廠商型號(hào)

R5F56604DDFB

功能描述

120-MHz 32-bit RX MCU, on-chip FPU, 709 CoreMark, Supportive of 5V power supply, up to 1-MB flash memory, up to 128-KB SRAM, 32-KB data flash memory, various communications interfaces, including CAN FD,12-bit A/D converter

文件大小

1.40989 Mbytes

頁(yè)面數(shù)量

123 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-11-20 9:20:00

R5F56604DDFB規(guī)格書(shū)詳情

Features

■ 32-bit RXv3 CPU core

? Maximum operating frequency: 120 MHz

Capable of 709 CoreMark in operation at 120 MHz

? A collective register bank save function is available.

? Supports the memory protection unit (MPU)

? JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

? Operation from a single 2.7- to 5.5-V supply

? Deep software standby mode with the RTC continuing to run

? Four low-power modes

■ On-chip code flash memory

? Supports versions with up to 1 Mbyte of ROM

? No waiting for access in 120-MHz operation

? User code is programmable by on-board or off-board programming.

? Programming/erasing as background operations (BGOs)

■ On-chip data flash memory

? 32 Kbytes, reprogrammable up to 100,000 times

? Programming/erasing as background operations (BGOs)

■ On-chip SRAM

? 128 Kbytes of SRAM (no wait states)

■ External address space

? Buses for full-speed data transfer (maximum operating frequency of

40 MHz)

? Four CS areas

? 8- or 16-bit bus space is selectable per area

■ Data transfer

? DMACAa: 8 channels

? DTCb: 1 channel

■ ELC

? Module operation can be initiated by event signals without using

interrupts

? Linked operation between modules is possible when the CPU is in

sleep mode

■ Reset and supply management

? Power-on reset (POR)

? Low voltage detection (LVD)

■ Clock functions

? The main clock oscillator is connectable to an 8- to 24-MHz external

crystal resonator and usable as the PLL reference clock.

? A sub-clock oscillator connectable to a 32.768-kHz crystal resonator

? Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz

? 120-kHz clock for the IWDTa

■ Real-time clock

? Adjustment functions (30 seconds, leap year, and error)

? Real-time clock counting and binary counting modes are selectable

? Time capture in response to an event-signal input

■ Independent watchdog timer

? 120-kHz IWDT-dedicated on-chip oscillator clock operation

■ Useful functions for IEC60730 compliance

? Oscillation-stoppage detection, functions for self-diagnosis and

detection of disconnection for the A/D converter, clock frequency

accuracy measurement circuit, independent watchdog timer, RAM

test-assisting function by DOC, and CRCA, etc.

? Register write protection function that protects important registers

against overwriting

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