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R5F56719HDFB中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

R5F56719HDFB
廠商型號(hào)

R5F56719HDFB

功能描述

120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,

文件大小

2.80649 Mbytes

頁(yè)面數(shù)量

178 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-11-19 17:24:00

R5F56719HDFB規(guī)格書詳情

■ 32-bit RXv3 CPU core

? Maximum operating frequency: 120 MHz

Capable of 707 CoreMark in operation at 120 MHz

? Double-precision 64-bit IEEE-754 floating point

? A collective register bank save function is available.

? Supports the memory protection unit (MPU)

? JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

? Operation from a single 2.7- to 3.6-V supply

? Battery supply of backup power allows continued operations of the

RTC and the backup registers.

? Four low-power modes

■ On-chip code flash memory

? Supports versions with up to 2 Mbytes of ROM

? No wait cycles at up to 60 MHz or when the ROM cache is hit, onewait

state at up to 120 MHz

? User code is programmable by on-board or off-board programming.

? Programming/erasing as background operations (BGOs)

? A dual-bank structure allows exchanging the start-up bank.

■ On-chip data flash memory

? 8 Kbytes, reprogrammable up to 100,000 times

? Programming/erasing as background operations (BGOs)

■ On-chip SRAM

? 384 Kbytes of SRAM (no wait states)

? 4 Kbytes of standby RAM (backup on deep software standby)

■ External address space

? Buses for full-speed data transfer (maximum operating frequency of

60 MHz)

? 8 CS areas

? 8- or 16-bit bus space is selectable per area

? Independent SDRAM area (128 Mbytes)

■ Data transfer

? DMACAb: 8 channels

? DTCb: 1 channel

? EXDMACa: 2 channels

■ Reset and supply management

? Power-on reset (POR)

? Low voltage detection (LVD) with voltage settings

? Backup domain low power detection

■ Clock functions

? External crystal resonator or internal PLL for operation at 8 to 24

MHz

? A sub-clock oscillator connectable to a 32.768-kHz crystal resonator

? Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz

? 120-kHz clock for the IWDTa

■ Real-time clock

? Adjustment functions (30 seconds, leap year, and error)

? Real-time clock counting and binary counting modes are selectable

? Time capture in response to an event-signal input

■ Independent watchdog timer

? Operates with the 120-kHz clock frequency generated by the

dedicated low-speed oscillator

■ Useful functions for IEC60730 compliance

? Oscillation-stoppage detection, frequency measurement, CRCA,

IWDTa, self-diagnostic function for the A/D converter, etc.

? Register write protection function that protects important registers

against overwriting

■ Remote control signal receiver

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