R7FA4M2AD3CFM中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

■ Arm? Cortex?-M33 Core

● Armv8-M architecture with the main extension

● Maximum operating frequency: 100 MHz

● Arm Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure and Non-secure instance

– Driven by LOCO or system clock

● CoreSight? ETM-M33

■ Memory

● Up to 512-KB code flash memory

● 8-KB data flash memory (100,000 program/erase (P/E) cycles)

● 128-KB SRAM

■ Connectivity

● Serial Communications Interface (SCI) × 6

– Asynchronous interfaces

– 8-bit clock synchronous interface

– Smart card interface

– Simple IIC

– Simple SPI

– Manchester coding (SCI3, SCI4)

● I2C bus interface (IIC) × 2

● Serial Peripheral Interface (SPI)

● Quad Serial Peripheral Interface (QSPI)

● USB 2.0 Full-Speed Module (USBFS)

● Control Area Network module (CAN)

● SD/MMC Host Interface (SDHI)

● Serial Sound Interface Enhanced (SSIE)

■ Analog

● 12-bit A/D Converter (ADC12)

● 12-bit D/A Converter (DAC12) × 2

● Temperature Sensor (TSN)

■ Timers

● General PWM Timer 32-bit (GPT32) × 4

● General PWM Timer 16-bit (GPT16) × 4

● Low Power Asynchronous General Purpose Timer (AGT) × 6

■ Security and Encryption

● Secure Crypto Engine 9

– Symmetric algorithms: AES

– Asymmetric algorithms: RSA, ECC, and DSA

– Hash-value generation: SHA224, SHA256, GHASH

– 128-bit unique ID

● Arm? TrustZone?

– Up to three regions for the code flash

– Up to two regions for the data flash

– Up to three regions for the SRAM

– Individual secure or non-secure security attribution for each peripheral

● Device lifecyle management

● Pin function

– Up to three tamper pins

– Secure pin multiplexing